November 13, 2000 -- 0-In Design Automation, Inc., the industry leader in white-box verification technology, today announced that its new release of 0-In Check and 0-In Search includes features to enhance functional verification for complex system-on-chip (SOC) devices. These features extend 0-In's support across a broader range of verification environments and design styles, making it easier than ever to incorporate 0-In's white-box verification products into an existing SOC design methodology.

Powerful Semiformal Technology Available to All
"0-In brings the power of formal verification to a simulation-based methodology," said 0-In CEO Dr. L. Curtis Widdoes. "Both 0-In Check and 0-In Search complement industry-standard simulation methods and products. Now, any engineer experienced in Verilog simulation methods can have access to 0-In's powerful verification technology."

0-In Check enhances existing simulations by monitoring for correct behavior of internal design structures; 0-In Search uses semiformal verification technology to amplify simulation tests and explore a wider range of legal design behavior. Both products use checkers and protocol monitors from 0-In's CheckerWare library to identify legal and illegal behavior within the design.

0-In Tools Integrate Seamlessly with Simulation
0-In Check and 0-In Search run alongside simulation, requiring only a single additional argument to the Verilog simulator. There is no need to add complicated, additional steps to current verification flows. The setup process is fully automated; users simply provide their simulation file lists to 0-In Check and it produces design-specific checkers ready to run in simulation or with 0-In Search.

Semiformal Verification Runs in Regression Mode
SOC verification suites include many simulation tests, often run in regression mode on a "farm" of compute servers. With the new release, 0-In Search may also be run in regression mode. "We have customers today who run on hundreds of servers at one time," observed Dr. Widdoes. "In response to their requests, we have added support so that all 0-In products can be set up to run automatically in regressions across a large server farm."

New Features Support Popular SOC Design Styles
0-In Check supports all design and clocking styles. In the new release, 0-In Search has been enhanced to support the full range of clocking styles typically used in SOC designs, including gated clocks and multiple synchronous clocks. In addition, the CheckerWare library has been enhanced to include new checkers for design structures popular in SOC architectures, including networking and telecommunications applications.

0-In Products Work with Popular Simulation Environments and Workstations
The new release of 0-In products supports the Model Technology ModelSim/VLOG simulator in addition to Synopsys (Nasdaq:SNPS) VCS and Cadence (Nasdaq: CDN) NC-Verilog and Verilog-XL. The release also adds support for the Debussy debug system from Novas. Both 0-In Check and 0-In Search have been qualified for Sun Microsystems' (Nasdaq: SUNW) new Sun BladeTM 1000 workstations and the Solaris™ 8 release.

About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") is a privately held electronic design automation (EDA) company that develops tools that zero-in on functional bugs in ASIC and IC designs. 0-In was founded in 1996 and is based in San Jose, CA, with sales offices in Boxborough, MA and Austin, TX plus distribution in Japan through Pacific Design Inc. Leading-edge companies that have adopted 0-In tools and methodologies include AMD, Fujitsu, Hitachi, Hughes, Lucent, Nortel, Sun and Tensilica. More information on 0-In is available at http://www.0-in.com

Contact: Steven D White, 0-In Design Automation, 408-487-3649, swhite@0-in.com